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Silicon Labs /SiM3_NRND /SIM3L168_A /ACCTR_0 /TIMING

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Interpret as TIMING

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0STATE0 (DISABLED)B0OEN 0 (DISABLED)B1OEN 0ZONED0ZONEC0ZONEB0ZONEA0ZONEP0 (DISABLED)WAKEMD 0 (DISABLED)START 0 (4_CYCLES)PERIOD

B1OEN=DISABLED, WAKEMD=DISABLED, B0OEN=DISABLED, START=DISABLED, PERIOD=4_CYCLES

Description

Timing

Fields

STATE

Timing State.
B0OEN

Bias 0 Offset Enable.

0 (DISABLED): The bias 0 pulse is a full width (minimum 2 RTC cycles).

1 (ENABLED): The bias 0 pulse is delayed 1/2 an RTC cycle and de-asserts 1/2 an RTC cycle early (minimum 3 RTC cycles).
B1OEN

Bias 1 Offset Enable.

0 (DISABLED): The bias 1 pulse is a full width (minimum 2 RTC cycles).

1 (ENABLED): The bias 1 pulse is delayed 1/2 an RTC cycle and de-asserts 1/2 an RTC cycle early (minimum 3 RTC cycles).
ZONED

Zone D Count.
ZONEC

Zone C Count.
ZONEB

Zone B Count.
ZONEA

Zone A Count.
ZONEP

Zone P Count.
WAKEMD

LC Wake Mode.

0 (DISABLED): Disable wake up events.

1 (WZONEP): Wake or interrupt at the start of zone P.

2 (WZONEA): Wake or interrupt at the start of zone A.

3 (WZONEB): Wake or interrupt at the start of zone B.

4 (WZONEC): Wake or interrupt at the start of zone C.

5 (WZONED): Wake or interrupt at the start of zone D.

6 (WEND): Wake or interrupt at the end of the LC sequence.

7 (WKSTOP): Wake or interrupt at the end of the LC sequence and stop the sequencer when this event occurs.
START

Sequencer Start.

0 (DISABLED): Do not start the sequencer.

1 (ENABLED): Start the sequencer.
PERIOD

Pulse Counter Period.

0 (4_CYCLES): Set the period to 4 RTC cycles.

1 (8_CYCLES): Set the period to 8 RTC cycles.

2 (16_CYCLES): Set the period to 16 RTC cycles.

3 (32_CYCLES): Set the period to 32 RTC cycles.

4 (64_CYCLES): Set the period to 64 RTC cycles.

5 (128_CYCLES): Set the period to 128 RTC cycles.

6 (256_CYCLES): Set the period to 256 RTC cycles.

7 (512_CYCLES): Set the period to 512 RTC cycles.

8 (1024_CYCLES): Set the period to 1024 RTC cycles.

9 (2048_CYCLES): Set the period to 2048 RTC cycles.

10 (4096_CYCLES): Set the period to 4096 RTC cycles.

14 (SINGLE_SAMPLE): Set the module to single sample mode and disable the period counter after the next completion of the sequencer. In this mode, firmware must start each sample by setting FLCSEN to 1.

15 (CONSECUTIVE_SAMPLE): Set the module to consecutive sample mode and disable the period counter. After completing zone D, the timing engine will jump directly to zone A, skipping both the W and P zones.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data